/* * This devicetree is generated by sopc2dts version rel_14.0_RC3 on Thu Sep 11 14:36:19 MYT 2014 * Sopc2dts is written by Walter Goossens * in cooperation with the nios2 community */ /dts-v1/; / { model = "ALTR,qsys_ghrd_4sgx230"; compatible = "ALTR,qsys_ghrd_4sgx230"; #address-cells = < 1 >; #size-cells = < 1 >; cpus { #address-cells = < 1 >; #size-cells = < 0 >; cpu: cpu@0x0 { device_type = "cpu"; compatible = "altr,nios2-14.0", "altr,nios2-1.0"; reg = < 0x00000000 >; interrupt-controller; #interrupt-cells = < 1 >; ALTR,exception-addr = < 3489660960 >; /* embeddedsw.dts.params.ALTR,exception-addr type NUMBER */ ALTR,fast-tlb-miss-addr = < 3355440128 >; /* embeddedsw.dts.params.ALTR,fast-tlb-miss-addr type NUMBER */ ALTR,has-div = < 1 >; /* embeddedsw.dts.params.ALTR,has-div type NUMBER */ ALTR,has-initda = < 1 >; /* embeddedsw.dts.params.ALTR,has-initda type NUMBER */ ALTR,has-mmu = < 1 >; /* embeddedsw.dts.params.ALTR,has-mmu type NUMBER */ ALTR,has-mul = < 1 >; /* embeddedsw.dts.params.ALTR,has-mul type NUMBER */ ALTR,has-mulx = < 1 >; /* embeddedsw.dts.params.ALTR,has-mulx type NUMBER */ ALTR,implementation = "fast"; /* embeddedsw.dts.params.ALTR,implementation type STRING */ ALTR,pid-num-bits = < 8 >; /* embeddedsw.dts.params.ALTR,pid-num-bits type NUMBER */ ALTR,reset-addr = < 3263168512 >; /* embeddedsw.dts.params.ALTR,reset-addr type NUMBER */ ALTR,tlb-num-entries = < 256 >; /* embeddedsw.dts.params.ALTR,tlb-num-entries type NUMBER */ ALTR,tlb-num-ways = < 16 >; /* embeddedsw.dts.params.ALTR,tlb-num-ways type NUMBER */ ALTR,tlb-ptr-sz = < 8 >; /* embeddedsw.dts.params.ALTR,tlb-ptr-sz type NUMBER */ clock-frequency = < 150000000 >; /* embeddedsw.dts.params.clock-frequency type NUMBER */ dcache-line-size = < 32 >; /* embeddedsw.dts.params.dcache-line-size type NUMBER */ dcache-size = < 32768 >; /* embeddedsw.dts.params.dcache-size type NUMBER */ icache-line-size = < 32 >; /* embeddedsw.dts.params.icache-line-size type NUMBER */ icache-size = < 32768 >; /* embeddedsw.dts.params.icache-size type NUMBER */ }; //end cpu@0x0 (cpu) }; //end cpus memory@0 { device_type = "memory"; reg = < 0x10000000 0x08000000 0x07FFF400 0x00000400 >; }; //end memory@0 sopc0: sopc@0 { device_type = "soc"; ranges; #address-cells = < 1 >; #size-cells = < 1 >; compatible = "ALTR,avalon", "simple-bus"; bus-frequency = < 150000000 >; pb_cpu_to_io: bridge@0x8000000 { compatible = "ALTR,avalon-14.0", "simple-bus"; reg = < 0x08000000 0x00800000 >; #address-cells = < 1 >; #size-cells = < 1 >; ranges = < 0x00004D00 0x08004D00 0x00000010 0x00002000 0x08002000 0x00002000 0x00004CE0 0x08004CE0 0x00000010 0x00004D50 0x08004D50 0x00000008 0x00004CC0 0x08004CC0 0x00000010 0x00004400 0x08004400 0x00000040 0x00004800 0x08004800 0x00000040 0x00004D40 0x08004D40 0x00000008 0x00400000 0x08400000 0x00000020 0x00004C80 0x08004C80 0x00000020 0x00004000 0x08004000 0x00000400 >; button_pio: gpio@0x4d00 { compatible = "altr,pio-14.0", "altr,pio-1.0"; reg = < 0x00004D00 0x00000010 >; interrupt-parent = < &cpu >; interrupts = < 9 >; altr,gpio-bank-width = < 3 >; /* embeddedsw.dts.params.altr,gpio-bank-width type NUMBER */ altr,interrupt_type = < 3 >; /* embeddedsw.dts.params.altr,interrupt_type type NUMBER */ edge_type = < 2 >; /* embeddedsw.dts.params.edge_type type NUMBER */ level_trigger = < 0 >; /* embeddedsw.dts.params.level_trigger type NUMBER */ resetvalue = < 0 >; /* embeddedsw.dts.params.resetvalue type NUMBER */ #gpio-cells = < 2 >; gpio-controller; }; //end gpio@0x4d00 (button_pio) tse_mac: ethernet@0x2000 { compatible = "altr,tse-14.0", "altr,tse-1.0"; reg = < 0x00004000 0x00000400 0x00004400 0x00000040 0x00004800 0x00000040 0x00002000 0x00002000 >; reg-names = "control_port", "rx_csr", "tx_csr", "s1"; interrupt-parent = < &cpu >; interrupts = < 2 3 >; interrupt-names = "rx_irq", "tx_irq"; ALTR,rx-fifo-depth = < 2048 >; /* embeddedsw.dts.params.ALTR,rx-fifo-depth type NUMBER */ ALTR,tx-fifo-depth = < 2048 >; /* embeddedsw.dts.params.ALTR,tx-fifo-depth type NUMBER */ rx-fifo-depth = < 8192 >; /* embeddedsw.dts.params.rx-fifo-depth type NUMBER */ tx-fifo-depth = < 8192 >; /* embeddedsw.dts.params.tx-fifo-depth type NUMBER */ address-bits = < 48 >; max-frame-size = < 1518 >; local-mac-address = [ 00 00 00 00 00 00 ]; altr,enable-sup-addr = < 0 >; altr,enable-hash = < 0 >; phy-mode = "sgmii"; ALTR,mii-id = < 0 >; phy-handle = < &phy0 >; tse_mac_mdio: mdio { compatible = "altr,tse-mdio"; #address-cells = < 1 >; #size-cells = < 0 >; phy0: ethernet-phy@0 { reg = < 0 >; device_type = "ethernet-phy"; }; }; //end mdio (tse_mac_mdio) }; //end ethernet@0x2000 (tse_mac) dipsw_pio: gpio@0x4ce0 { compatible = "altr,pio-14.0", "altr,pio-1.0"; reg = < 0x00004CE0 0x00000010 >; interrupt-parent = < &cpu >; interrupts = < 8 >; altr,gpio-bank-width = < 8 >; /* embeddedsw.dts.params.altr,gpio-bank-width type NUMBER */ altr,interrupt_type = < 3 >; /* embeddedsw.dts.params.altr,interrupt_type type NUMBER */ edge_type = < 2 >; /* embeddedsw.dts.params.edge_type type NUMBER */ level_trigger = < 0 >; /* embeddedsw.dts.params.level_trigger type NUMBER */ resetvalue = < 0 >; /* embeddedsw.dts.params.resetvalue type NUMBER */ #gpio-cells = < 2 >; gpio-controller; }; //end gpio@0x4ce0 (dipsw_pio) jtag_uart: serial@0x4d50 { compatible = "altr,juart-14.0", "altr,juart-1.0"; reg = < 0x00004D50 0x00000008 >; interrupt-parent = < &cpu >; interrupts = < 1 >; }; //end serial@0x4d50 (jtag_uart) led_pio: gpio@0x4cc0 { compatible = "altr,pio-14.0", "altr,pio-1.0"; reg = < 0x00004CC0 0x00000010 >; altr,gpio-bank-width = < 16 >; /* embeddedsw.dts.params.altr,gpio-bank-width type NUMBER */ resetvalue = < 0 >; /* embeddedsw.dts.params.resetvalue type NUMBER */ #gpio-cells = < 2 >; gpio-controller; }; //end gpio@0x4cc0 (led_pio) sysid: sysid@0x4d40 { compatible = "altr,sysid-14.0", "altr,sysid-1.0"; reg = < 0x00004D40 0x00000008 >; id = < 0 >; /* embeddedsw.dts.params.id type NUMBER */ timestamp = < 1404095069 >; /* embeddedsw.dts.params.timestamp type NUMBER */ }; //end sysid@0x4d40 (sysid) timer_1ms: timer@0x400000 { compatible = "altr,timer-14.0", "altr,timer-1.0"; reg = < 0x00400000 0x00000020 >; interrupt-parent = < &cpu >; interrupts = < 11 >; clock-frequency = < 150000000 >; /* embeddedsw.dts.params.clock-frequency type NUMBER */ }; //end timer@0x400000 (timer_1ms) uart: serial@0x4c80 { compatible = "altr,uart-14.0", "altr,uart-1.0"; reg = < 0x00004C80 0x00000020 >; interrupt-parent = < &cpu >; interrupts = < 10 >; clock-frequency = < 150000000 >; /* embeddedsw.dts.params.clock-frequency type NUMBER */ current-speed = < 115200 >; /* embeddedsw.dts.params.current-speed type NUMBER */ }; //end serial@0x4c80 (uart) }; //end bridge@0x8000000 (pb_cpu_to_io) ext_flash: flash@0x0 { compatible = "ALTR,cfi_flash-14.0", "cfi-flash"; reg = < 0x00000000 0x02000000 >; bank-width = < 2 >; device-width = < 1 >; }; //end flash@0x0 (ext_flash) ext_flash_1: flash@0x2000000 { compatible = "ALTR,cfi_flash-14.0", "cfi-flash"; reg = < 0x02000000 0x02000000 >; bank-width = < 2 >; device-width = < 1 >; }; //end flash@0x2000000 (ext_flash_1) }; //end sopc@0 (sopc0) chosen { bootargs = "debug console=ttyJ0,115200"; }; //end chosen }; //end /