c8[([Altera SOCFPGA Cyclone V#altr,socfpga-cyclone5altr,socfpga aliases,/sopc@0/ethernet@0xff702000cpus 6altr,socfpga-smpcpu@0x0Dcpu!arm,cortex-a9-16.1arm,cortex-a9PTcpu@0x1Dcpu!arm,cortex-a9-16.1arm,cortex-a9PTmemoryDmemoryPclocks clk_0 fixed-clocker clk_0-clkvid_clk fixed-clockerl vid_clk-clkhps_0_eosc1 fixed-clocker}x@hps_0_eosc1-clkhps_0_eosc2 fixed-clocker}x@hps_0_eosc2-clkhps_0_f2s_periph_ref_clk fixed-clockerhps_0_f2s_periph_ref_clk-clkhps_0_f2s_sdram_ref_clk fixed-clockerhps_0_f2s_sdram_ref_clk-clk  sopc@0Dsoc ALTR,avalonsimple-busbridge@0xc0000000altr,bridge-16.1simple-busP axi_h2faxi_h2f_lw 0h2f_axi_clockh2f_lw_axi_clockf2h_sdram0_clock &'&&&&@&@ serial@0x100060000altr,juart-16.1altr,juart-1.0 P *ilc@0x100070000"altr,altera_ilc-16.1altr,ilc-1.0 P$()*dipsw_piobutton_piojtag_uart' vip@0x1000601005ALTR,vip-frame-reader-14.0ALTR,vip-frame-reader-9.1 P ,clock_resetclock_master:DO^n~sysid@0x100060008altr,sysid-16.1altr,sysid-1.0 PYGgpio@0x1000600c0altr,pio-16.1altr,pio-1.0 P )gpio@0x100060080altr,pio-16.1altr,pio-1.0 P (gpio@0x100060040altr,pio-16.1altr,pio-1.0 P@ //intc@0xfffed000)arm,cortex-a9-gic-16.1arm,cortex-a9-gicPaxi_slave0axi_slave1L2-cache@0xfffef000%arm,pl310-cache-16.1arm,pl310-cacheP &" 0 @dma@0xffe01000'arm,pl330-16.1arm,pl330arm,primecellP hQ\j  apb_pclkx  sysmgr@0xffd08000&altr,sys-mgr-16.1altr,sys-mgrsysconPЀЀ++clkmgr@0xffd04000altr,clk-mgr-16.1altr,clk-mgrP@ 1eosc1eosc2f2s_periph_ref_clkf2s_sdram_ref_clkclock_tree sdram_pllaltr,socfpga-pll-clockP  0hps_0_eosc1hps_0_eosc2hps_0_f2s_sdram_ref_clke   ddr_dqs_clkaltr,socfpga-perip-clkP eddr_2x_dqs_clkaltr,socfpga-perip-clkP eddr_dq_clkaltr,socfpga-perip-clkP es2f_usr2_clkaltr,socfpga-perip-clkP eperiph_pllaltr,socfpga-pll-clockP 1hps_0_eosc1hps_0_eosc2hps_0_f2s_periph_ref_clke   per_nand_mmc_clkaltr,socfpga-perip-clkP eper_base_clkaltr,socfpga-perip-clkP eper_qspi_clkaltr,socfpga-perip-clkP es2f_usr1_clkaltr,socfpga-perip-clkP eemac0_clkaltr,socfpga-perip-clkP eemac1_clkaltr,socfpga-perip-clkP emain_pllaltr,socfpga-pll-clockP@e   cfg_s2f_usr0_clkaltr,socfpga-perip-clkP\ emain_qspi_clkaltr,socfpga-perip-clkPT edbg_base_clkaltr,socfpga-perip-clkPP main_pllhps_0_eosc1e  mpuclkaltr,socfpga-perip-clkPH e    mainclkaltr,socfpga-perip-clkPL e  main_nand_sdmmc_clkaltr,socfpga-perip-clkPX empu_l2_ram_clkaltr,socfpga-gate-clk el4_main_clkaltr,socfpga-gate-clke`l3_mp_clkaltr,socfpga-gate-clke` dl3_sp_clkaltr,socfpga-gate-clke dl4_mp_clkaltr,socfpga-gate-clkmainclkper_base_clke` d  l4_sp_clkaltr,socfpga-gate-clkmainclkper_base_clke` d!!dbg_at_clkaltr,socfpga-gate-clke` hdbg_clkaltr,socfpga-gate-clke` hdbg_trace_clkaltr,socfpga-gate-clke` ldbg_timer_clkaltr,socfpga-gate-clke`cfg_clkaltr,socfpga-gate-clke`h2f_user0_clockaltr,socfpga-gate-clke` emac_0_clkaltr,socfpga-gate-clkeemac_1_clkaltr,socfpga-gate-clkeusb_mp_clkaltr,socfpga-gate-clke ((spi_m_clkaltr,socfpga-gate-clke ##can0_clkaltr,socfpga-gate-clke ,,can1_clkaltr,socfpga-gate-clke  --gpio_db_clkaltr,socfpga-gate-clke h2f_user1_clockaltr,socfpga-gate-clkesdmmc_clkaltr,socfpga-gate-clk >hps_0_f2s_periph_ref_clkmain_nand_sdmmc_clkper_nand_mmc_clkenand_x_clkaltr,socfpga-gate-clk >hps_0_f2s_periph_ref_clkmain_nand_sdmmc_clkper_nand_mmc_clke nand_clkaltr,socfpga-gate-clk >hps_0_f2s_periph_ref_clkmain_nand_sdmmc_clkper_nand_mmc_clke ""qspi_clkaltr,socfpga-gate-clk 4hps_0_f2s_periph_ref_clkmain_qspi_clkper_qspi_clke $$ddr_dqs_clk_gatealtr,socfpga-gate-clkeddr_2x_dqs_clk_gatealtr,socfpga-gate-clkeddr_dq_clk_gatealtr,socfpga-gate-clkeh2f_user2_clockaltr,socfpga-gate-clkel3_main_clkaltr,socfpga-gate-clkempu_periph_clkaltr,socfpga-perip-clk eP..sdmmc_clk_dividedealtr,socfpga-gate-clk%%rstmgr@0xffd05000&altr,rst-mgr-16.1altr,rst-mgrsysconPP**fpgamgr@0xff7060007altr,fpga-mgr-16.1altr,fpga-mgraltr,socfpga-fpga-mgrPp`axi_slave0axi_slave1 mmio serial@0xffc02000'snps,dw-apb-uart-16.1snps,dw-apb-uartP  ! okayserial@0xffc03000'snps,dw-apb-uart-16.1snps,dw-apb-uartP0 !  disabledtimer@0xffc08000/snps,dw-apb-timer-sp-16.1snps,dw-apb-timer-spP !timertimer@0xffc09000/snps,dw-apb-timer-sp-16.1snps,dw-apb-timer-spP !timertimer@0xffd000001snps,dw-apb-timer-osc-16.1snps,dw-apb-timer-oscP timertimer@0xffd010001snps,dw-apb-timer-osc-16.1snps,dw-apb-timer-oscP timertimer@0xffd02000snps,dw-wdt-16.1snps,dw-wdtP  timertimer@0xffd03000snps,dw-wdt-16.1snps,dw-wdtP0 timer disabledgpio@0xff7080000snps,dw-apb-gpiosnps,dw-gpio-16.1snps,dw-gpioPp   gpio-controller@0snps,dw-apb-gpio-portP gpio@0xff7090000snps,dw-apb-gpiosnps,dw-gpio-16.1snps,dw-gpioPp   gpio-controller@0snps,dw-apb-gpio-portP &&gpio@0xff70a0000snps,dw-apb-gpiosnps,dw-gpio-16.1snps,dw-gpioPp   gpio-controller@0snps,dw-apb-gpio-portP i2c@0xffc04000-snps,designware-i2c-16.1snps,designware-i2cP@ !(okay >rIaatmel,24c32@0x51 atmel,24c32PQy dallas,ds1339@0x68dallas,ds1339Phi2c@0xffc05000-snps,designware-i2c-16.1snps,designware-i2cPP !(okayi2c@0xffc06000-snps,designware-i2c-16.1snps,designware-i2cP` !( disabledi2c@0xffc07000-snps,designware-i2c-16.1snps,designware-i2cPp !( disabledflash@0xff900000'denali,nand-16.1denali,denali-nand-dtPnand_datadenali_reg "  disabledspi@0xfff000007snps,dw-spi-mmio-16.1snps,dw-spi-mmiosnps,dw-apb-ssiP #  disabledspidev@0rohm,dh2228fvPspi@0xfff010007snps,dw-spi-mmio-16.1snps,dw-spi-mmiosnps,dw-apb-ssiP #  disabledflash@0xff705000-cadence,qspi-16.1cadence,qspicdns,qspi-norPpPaxi_slave0axi_slave1 $/okay ׄn25q512a@0 n25q512a P2 2&5E2S2aopartition@0}Flash 0 Raw DataPpartition@800000}Flash 1 jffs2 FilesystemPflash@0xff704000altr,socfpga-dw-mshcPp@  %biuciu/okay  & & ''slot@0Pusb@0xffb00000)snps,dwc-otg-16.1snps,dwc-otgsnps,dwc2P }(otg&>><512 512 512 512 512 512 512 512 512 512 512 512 512 512 512>U>f<512 512 512 512 512 512 512 512 512 512 512 512 512 512 512>w    usb2-phy disabledusb@0xffb40000)snps,dwc-otg-16.1snps,dwc-otgsnps,dwc2P (otg&>><512 512 512 512 512 512 512 512 512 512 512 512 512 512 512>U>f<512 512 512 512 512 512 512 512 512 512 512 512 512 512 512>w    usb2-phyokay)ethernet@0xff700000Dsynopsys,dwmac-16.1altr,socfpga-stmmacsnps,dwmac-3.70asnps,dwmacPp  s stmmacethmacirq ' disabledCQ0^m stmmaceth* ethernet@0xff702000Dsynopsys,dwmac-16.1altr,socfpga-stmmacsnps,dwmac-3.70asnps,dwmacPp  x stmmacethmacirq 'okayCQ0^mrgmii  )6 C+` stmmaceth*!can@0xffc00000bosch,dcan-16.1bosch,d_canP$interrupt_sender0interrupt_sender1, disabledcan@0xffc01000bosch,dcan-16.1bosch,d_canP$interrupt_sender0interrupt_sender1- disabledrl3regs@0xff800000$altr,l3regs-16.1altr,l3regssysconPsdr-ctl@0xffc25000&altr,sdr-ctl-16.1altr,sdr-ctlsysconPPtimer@0xfffec6005arm,cortex-a9-twd-timer-16.1arm,cortex-a9-twd-timerP  .scu@0xfffec000(arm,corex-a9-scu-16.1arm,cortex-a9-scuPvcc3p3-regulatorregulator-fixedV3.3Ve2Z}2Z''leds gpio-ledshps0 }hps_led0 "&hps1 }hps_led1 "&hps2 }hps_led2 "& hps3 }hps_led3 "& fpga0 }fpga_led0 "/fpga1 }fpga_led1 "/fpga2 }fpga_led2 "/fpga3 }fpga_led3 "/pmu0 arm,cortex-a9-pmucti0@ff118000arm,coresight-ctiPcti0@ff119000arm,coresight-ctiPfpgabridge@0altr,socfpga-hps2fpga-bridge }hps2fpga hps2fpga*`fpgabridge@1altr,socfpga-lwhps2fpga-bridge }lwhps2fpga lwhps2fpga*afpgabridge@2altr,socfpga-fpga2hps-bridge }fpga2hps fpga2hps*bfpgabridge@3altr,socfpga-fpga2sdram-bridge }fpga2sdramusbphy@0usb-nop-xceivokay))chosenconsole=ttyS0,115200 modelcompatible#address-cells#size-cellsethernet0enable-methoddevice_typeregnext-level-cache#clock-cellsclock-frequencyclock-output-nameslinux,phandlerangesbus-frequencyreg-namesclocksclock-namesinterrupt-parentinterruptsinterrupt-namesinterrupt-controller#interrupt-cellsaltr,sw-fifo-depthmax-widthmax-heightbits-per-colorcolors-per-beatbeats-per-pixelmem-word-widthidtimestampaltr,gpio-bank-widthaltr,interrupt-typealtr,interrupt_typeedge_typelevel_triggerresetvalue#gpio-cellsgpio-controllercache-levelcache-unifiedarm,tag-latencyarm,data-latency#dma-cells#dma-channels#dma-requestscopy-alignnr-irqsnr-valid-pericpu1-start-addrdiv-regfixed-dividerclk-gateclk-phase#reset-cellsaltr,modrst-offsettransportreg-io-widthreg-shiftstatussnps,nr-gpiosemptyfifo_hold_masterspeed-modei2c-sda-falling-time-nsi2c-scl-falling-time-nspagesizedevice-widthbus-numnum-chipselectspi-max-frequencyenable-dmamaster-ref-clkext-decoderm25p,fast-readpage-sizeblock-sizetshsl-nstsd2d-nstchsh-nstslch-nscdns,page-sizecdns,block-sizecdns,tshsl-nscdns,tsd2d-nscdns,tchsh-nscdns,tslch-nslabelnum-slotsbroken-cdcap-mmc-highspeedcap-sd-highspeedbus-widthaltr,dw-mshc-ciu-divaltr,dw-mshc-sdr-timingsupports-highspeedcd-gpiosvmmc-supplyvqmmc-supplydev-nperio-tx-fifo-sizedev-perio-tx-fifo-sizedev-rx-fifo-sizedev-tx-fifo-sizedma-maskenable-dynamic-fifohost-nperio-tx-fifo-sizehost-perio-tx-fifo-sizehost-rx-fifo-sizephy-namesulpi-ddrvoltage-switchphysrx-fifo-depthsnps,multicast-filter-binssnps,perfect-filter-entriestx-fifo-depthaddress-bitsmax-frame-sizelocal-mac-addressreset-namesresetsphy-modesnps,phy-addrtxc-skew-psrxc-skew-pstxen-skew-psrxdv-skew-psrxd0-skew-psrxd1-skew-psrxd2-skew-psrxd3-skew-pstxd0-skew-pstxd1-skew-pstxd2-skew-pstxd3-skew-psaltr,sysmgr-sysconregulator-nameregulator-min-microvoltregulator-max-microvoltread-ports-maskwrite-ports-maskcmd-ports-mask#phy-cellsbootargs