`8Y(YAltera SOCFPGA Cyclone V#altr,socfpga-cyclone5altr,socfpga aliases,/sopc@0/ethernet@0xff702000cpus cpu@0x06cpu!arm,cortex-a9-15.1arm,cortex-a9BFcpu@0x16cpu!arm,cortex-a9-15.1arm,cortex-a9BFmemory6memoryBclocks clk_0 fixed-clockWd tclk_0-clkvid_clk fixed-clockWd tvid_clk-clkhps_0_eosc1 fixed-clockWd}x@thps_0_eosc1-clkhps_0_eosc2 fixed-clockWd}x@thps_0_eosc2-clkhps_0_f2s_periph_ref_clk fixed-clockWdthps_0_f2s_periph_ref_clk-clkhps_0_f2s_sdram_ref_clk fixed-clockWdthps_0_f2s_sdram_ref_clk-clk  sopc@06soc ALTR,avalonsimple-busbridge@0xc0000000altr,bridge-15.1simple-busB axi_h2faxi_h2f_lw 0h2f_axi_clockh2f_lw_axi_clockf2h_sdram0_clock #@ @ !0 0    vip@0x1000300005ALTR,vip-frame-reader-14.0ALTR,vip-frame-reader-9.1 B +clock_resetclock_master'serial@0x100000140altr,juart-15.1altr,juart-1.0 B@ *ilc@0x100000000"altr,altera_ilc-15.1altr,ilc-1.0 B$()*6dipsw_piobutton_piojtag_uartF[l sysid@0x100010000altr,sysid-15.1altr,sysid-1.0 BVgpio@0x100000130altr,pio-15.1altr,pio-1.0 B0 )gpio@0x100000120altr,pio-15.1altr,pio-1.0 B  (gpio@0x100000100altr,pio-15.1altr,pio-1.0 B --intc@0xfffed000)arm,cortex-a9-gic-15.1arm,cortex-a9-gicBaxi_slave0axi_slave1F[L2-cache@0xfffef000%arm,pl310-cache-15.1arm,pl310-cacheB & " 2dma@0xffe01000'arm,pl330-15.1arm,pl330arm,primecellB hCN\  apb_pclkju } sysmgr@0xffd08000&altr,sys-mgr-15.1altr,sys-mgrsysconBЀЀ((clkmgr@0xffd04000altr,clk-mgr-15.1altr,clk-mgrB@ 1eosc1eosc2f2s_periph_ref_clkf2s_sdram_ref_clkclock_tree sdram_pllaltr,socfpga-pll-clockB  0hps_0_eosc1hps_0_eosc2hps_0_f2s_sdram_ref_clkW   ddr_dqs_clkaltr,socfpga-perip-clkB Wddr_2x_dqs_clkaltr,socfpga-perip-clkB Wddr_dq_clkaltr,socfpga-perip-clkB Ws2f_usr2_clkaltr,socfpga-perip-clkB Wperiph_pllaltr,socfpga-pll-clockB 1hps_0_eosc1hps_0_eosc2hps_0_f2s_periph_ref_clkW   per_nand_mmc_clkaltr,socfpga-perip-clkB Wper_base_clkaltr,socfpga-perip-clkB Wper_qspi_clkaltr,socfpga-perip-clkB Ws2f_usr1_clkaltr,socfpga-perip-clkB Wemac0_clkaltr,socfpga-perip-clkB Wemac1_clkaltr,socfpga-perip-clkB Wmain_pllaltr,socfpga-pll-clockB@W   cfg_s2f_usr0_clkaltr,socfpga-perip-clkB\ Wmain_qspi_clkaltr,socfpga-perip-clkBT Wdbg_base_clkaltr,socfpga-perip-clkBP main_pllhps_0_eosc1W  mpuclkaltr,socfpga-perip-clkBH W    mainclkaltr,socfpga-perip-clkBL W  main_nand_sdmmc_clkaltr,socfpga-perip-clkBX Wmpu_l2_ram_clkaltr,socfpga-gate-clk Wl4_main_clkaltr,socfpga-gate-clkW`l3_mp_clkaltr,socfpga-gate-clkW` dl3_sp_clkaltr,socfpga-gate-clkW dl4_mp_clkaltr,socfpga-gate-clkmainclkper_base_clkW` d  l4_sp_clkaltr,socfpga-gate-clkmainclkper_base_clkW` ddbg_at_clkaltr,socfpga-gate-clkW` hdbg_clkaltr,socfpga-gate-clkW` hdbg_trace_clkaltr,socfpga-gate-clkW` ldbg_timer_clkaltr,socfpga-gate-clkW`cfg_clkaltr,socfpga-gate-clkW`h2f_user0_clockaltr,socfpga-gate-clkW` emac_0_clkaltr,socfpga-gate-clkWemac_1_clkaltr,socfpga-gate-clkWusb_mp_clkaltr,socfpga-gate-clkW %%spi_m_clkaltr,socfpga-gate-clkW ""can0_clkaltr,socfpga-gate-clkW ))can1_clkaltr,socfpga-gate-clkW  **gpio_db_clkaltr,socfpga-gate-clkW h2f_user1_clockaltr,socfpga-gate-clkWsdmmc_clkaltr,socfpga-gate-clk >hps_0_f2s_periph_ref_clkmain_nand_sdmmc_clkper_nand_mmc_clkW$$nand_x_clkaltr,socfpga-gate-clk >hps_0_f2s_periph_ref_clkmain_nand_sdmmc_clkper_nand_mmc_clkW nand_clkaltr,socfpga-gate-clk >hps_0_f2s_periph_ref_clkmain_nand_sdmmc_clkper_nand_mmc_clkW !!qspi_clkaltr,socfpga-gate-clk 4hps_0_f2s_periph_ref_clkmain_qspi_clkper_qspi_clkW ##ddr_dqs_clk_gatealtr,socfpga-gate-clkWddr_2x_dqs_clk_gatealtr,socfpga-gate-clkWddr_dq_clk_gatealtr,socfpga-gate-clkWh2f_user2_clockaltr,socfpga-gate-clkWl3_main_clkaltr,socfpga-gate-clkWmpu_periph_clkaltr,socfpga-perip-clk WB++rstmgr@0xffd05000&altr,rst-mgr-15.1altr,rst-mgrsysconBP''fpgamgr@0xff706000!altr,fpga-mgr-15.1altr,fpga-mgrBp`axi_slave0axi_slave1 mmioserial@0xffc02000'snps,dw-apb-uart-15.1snps,dw-apb-uartB  okayserial@0xffc03000'snps,dw-apb-uart-15.1snps,dw-apb-uartB0  disabledtimer@0xffc08000/snps,dw-apb-timer-sp-15.1snps,dw-apb-timer-spB timertimer@0xffc09000/snps,dw-apb-timer-sp-15.1snps,dw-apb-timer-spB timertimer@0xffd000001snps,dw-apb-timer-osc-15.1snps,dw-apb-timer-oscB timertimer@0xffd010001snps,dw-apb-timer-osc-15.1snps,dw-apb-timer-oscB timertimer@0xffd02000snps,dw-wdt-15.1snps,dw-wdtB  timertimer@0xffd03000snps,dw-wdt-15.1snps,dw-wdtB0 timer disabledgpio@0xff7080000snps,dw-apb-gpiosnps,dw-gpio-15.1snps,dw-gpioBp   gpio-controller@0snps,dw-apb-gpio-portBF[ gpio@0xff7090000snps,dw-apb-gpiosnps,dw-gpio-15.1snps,dw-gpioBp   gpio-controller@0snps,dw-apb-gpio-portBF[ ,,gpio@0xff70a0000snps,dw-apb-gpiosnps,dw-gpio-15.1snps,dw-gpioBp   gpio-controller@0snps,dw-apb-gpio-portBF[ i2c@0xffc04000-snps,designware-i2c-15.1snps,designware-i2cB@ okay d6atmel,24c32@0x51 atmel,24c32BQN dallas,ds1339@0x68dallas,ds1339Bhi2c@0xffc05000-snps,designware-i2c-15.1snps,designware-i2cBP okayi2c@0xffc06000-snps,designware-i2c-15.1snps,designware-i2cB`  disabledi2c@0xffc07000-snps,designware-i2c-15.1snps,designware-i2cBp  disabledflash@0xff900000'denali,nand-15.1denali,denali-nand-dtBnand_datadenali_reg !  disabledWspi@0xfff000007snps,dw-spi-mmio-15.1snps,dw-spi-mmiosnps,dw-apb-ssiB " dl disabledspidev@0spidevB{spi@0xfff010007snps,dw-spi-mmio-15.1snps,dw-spi-mmiosnps,dw-apb-ssiB " dl disabledspidev@0spidevB{flash@0xff705000-cadence,qspi-15.1cadence,qspicdns,qspi-norBpPaxi_slave0axi_slave1 #dtlokayW ׄn25q512a@0 n25q512a B{22 2(26Dpartition@0RFlash 0 Raw DataBpartition@800000RFlash 1 jffs2 FilesystemBflash@0xff704000altr,socfpga-dw-mshcBp@  $biuciutXokayW buslot@0Busb@0xffb00000)snps,dwc-otg-15.1snps,dwc-otgsnps,dwc2B }%otg><512 512 512 512 512 512 512 512 512 512 512 512 512 512 512>><512 512 512 512 512 512 512 512 512 512 512 512 512 512 512>$ = U  gusb2-phy disabledqzusb@0xffb40000)snps,dwc-otg-15.1snps,dwc-otgsnps,dwc2B %otg><512 512 512 512 512 512 512 512 512 512 512 512 512 512 512>><512 512 512 512 512 512 512 512 512 512 512 512 512 512 512>$ = U  gusb2-phyokayqz&ethernet@0xff700000Dsynopsys,dwmac-15.1altr,socfpga-stmmacsnps,dwmac-3.70asnps,dwmacBp  s stmmaceth6macirq disabled0 stmmaceth' ethernet@0xff702000Dsynopsys,dwmac-15.1altr,socfpga-stmmacsnps,dwmac-3.70asnps,dwmacBp  x stmmaceth6macirqokay0"rgmii+09 E Q^kx (` stmmaceth'!can@0xffc00000bosch,dcan-15.1bosch,d_canB$6interrupt_sender0interrupt_sender1) disabledcan@0xffc01000bosch,dcan-15.1bosch,d_canB$6interrupt_sender0interrupt_sender1* disabledrl3regs@0xff800000$altr,l3regs-15.1altr,l3regssysconBsdr-ctl@0xffc25000&altr,sdr-ctl-15.1altr,sdr-ctlsysconBPtimer@0xfffec6005arm,cortex-a9-twd-timer-15.1arm,cortex-a9-twd-timerB  +scu@0xfffec000(arm,corex-a9-scu-15.1arm,cortex-a9-scuBleds gpio-ledshps0 Rhps_led0 ,hps1 Rhps_led1 ,hps2 Rhps_led2 , hps3 Rhps_led3 , fpga0 Rfpga_led0 -fpga1 Rfpga_led1 -fpga2 Rfpga_led2 -fpga3 Rfpga_led3 -pmu0 arm,cortex-a9-pmucti0@ff118000arm,coresight-ctiBcti0@ff119000arm,coresight-ctiBfpgabridge@0altr,socfpga-hps2fpga-bridge Rhps2fpga hps2fpga'`fpgabridge@1altr,socfpga-lwhps2fpga-bridge Rlwhps2fpga lwhps2fpga'afpgabridge@2altr,socfpga-fpga2hps-bridge Rfpga2hps fpga2hps'busbphy@0usb-nop-xceivokay&&chosenconsole=ttyS0,115200 modelcompatible#address-cells#size-cellsethernet0device_typeregnext-level-cache#clock-cellsclock-frequencyclock-output-nameslinux,phandlerangesbus-frequencyreg-namesclocksclock-namesinterrupt-parentinterruptsmax-widthmax-heightbits-per-colorcolors-per-beatbeats-per-pixelmem-word-widthinterrupt-namesinterrupt-controller#interrupt-cellsaltr,sw-fifo-depthidtimestampaltr,gpio-bank-widthaltr,interrupt-typealtr,interrupt_typeedge_typelevel_triggerresetvalue#gpio-cellsgpio-controllercache-levelcache-unifiedarm,tag-latencyarm,data-latency#dma-cells#dma-channels#dma-requestscopy-alignnr-irqsnr-valid-pericpu1-start-addrdiv-regfixed-dividerclk-gate#reset-cellstransportreg-io-widthreg-shiftstatussnps,nr-gpiosemptyfifo_hold_masterspeed-modei2c-sda-falling-time-nsi2c-scl-falling-time-nspagesizedevice-widthbus-numnum-chipselectspi-max-frequencyenable-dmamaster-ref-clkext-decoderm25p,fast-readpage-sizeblock-sizetshsl-nstsd2d-nstchsh-nstslch-nscdns,page-sizecdns,block-sizecdns,tshsl-nscdns,tsd2d-nscdns,tchsh-nscdns,tslch-nslabelnum-slotssupports-highspeedbroken-cdaltr,dw-mshc-ciu-divaltr,dw-mshc-sdr-timingbus-widthdev-nperio-tx-fifo-sizedev-perio-tx-fifo-sizedev-rx-fifo-sizedev-tx-fifo-sizedma-maskenable-dynamic-fifohost-nperio-tx-fifo-sizehost-perio-tx-fifo-sizehost-rx-fifo-sizephy-namesulpi-ddrvoltage-switchphysrx-fifo-depthsnps,multicast-filter-binssnps,perfect-filter-entriestx-fifo-depthaddress-bitsmax-frame-sizelocal-mac-addressreset-namesresetsphy-modesnps,phy-addrtxc-skew-psrxc-skew-pstxen-skew-psrxdv-skew-psrxd0-skew-psrxd1-skew-psrxd2-skew-psrxd3-skew-pstxd0-skew-pstxd1-skew-pstxd2-skew-pstxd3-skew-psaltr,sysmgr-syscon#phy-cellsbootargs