Compiling Hardware Design

How to re-compile the hardware design

Overview

This page presents how to re-compile the hardware design that comes with SoC EDS 16.0. This may be needed in case any changes are made to the design. Otherwise the pre-compiled design can be used as-is.

Prerequisites

The following items are required:

• Host PC running Linux (CentOS 6.5 or Ubuntu 12.04LTS)
• Altera Quartus™ Prime v16.0 b211 - http://www.altera.com/products/software/sfw-index.jsp
• GHRD v16.0 Archive from
  • https://releases.rocketboards.org/2016.05/gsrd/hw - for Rev C board
  • https://releases.rocketboards.org/2016.05/gsrd/hw/a10_devkit_revb/ - for Rev B board

Compiling Hardware Design

1. Retrieve and the archive file a10_soc_devkit_ghrd.tar.gz containing the hardware design and save it in the home folder. The file is available at

• • https://releases.rocketboards.org/2016.05/gsrd/hw - for Rev C board
  • https://releases.rocketboards.org/2016.05/gsrd/hw/a10_devkit_revb/ - for Rev B board

2. Extract the files from the archive

$ cd ~
$ tar xzf a10_soc_devkit_ghrd.tar.gz

3. Start Quartus Prime

$ ~/altera/16.0/quartus/bin/quartus --64bit

4. In Quartus open the hardware project by going to File → Open Project ... Then browse to ~a10_soc_devkit_ghrd/ghrd_10as066n2.qpf and click Open.

5. In Quartus, start Qsys by going to Tools → Qsys.

6. The tool will ask to select a file to open. Select the file ~/a10_soc_devkit_ghrd/ghrd_10as066n2.qsys and click Open.

7. QSys will load the file, displaying a progress bar. Once file is loaded, Qsys will display the system.

8. In Qsys, click the Generate HDL ... button on the bottom right corner. The Generation window will open. Click Generate button on bottom right corner.

9. Qsys will generate the system, displaying a progress bar.

10. Once complete, Qsys will display the "Generate Completed" message. Click Close to close the Generate window and get back to main Qsys window.

11. Click Finish to close the Qsys window and get back to main Quartus window.

12. In Quartus, start a compilation by going to Processing → Start Compilation. Then Quartus will compile the project

13. When compilation is completed, Quartus will display the status.

The following will be created:

• ~/a10_soc_devkit_ghrd/output_files/ghrd_10as066n2.sof - FPGA configuration file
• ~/a10_soc_devkit_ghrd/hps_isw_handoff - handoff folder, containing XML files used to generate the U-Boot device tree

Convert Programming File

The sof file produced by compiling the hardware design needs to be converted to the rbf format required by the U-Boot. It is also split into two different files:

• peripheral file - for configuring the IO ring
• core file - for configuring the FPGA fabric

The required steps are:

1. Start an embedded command shell

$ ~/altera/16.0/embedded/embedded_command_shell.sh

2. Go to the GHRD folder

$ cd ~/a10_soc_devkit_ghrd/

3. Convert the file

$ quartus_cpf -c -o bitstream_compression=on output_files/ghrd_10as066n2.sof output_files/ghrd_10as066n2.rbf

This will create the following files in the ~/a10_soc_devkit_ghrd/output_files/ folder:

• ghrd_10as066n2.periph.rbf - IO ring configuration file
• ghrd_10as066n2.core.rbf - FPGA fabric configuration file