15 December 2015 - 08:11
|
Version 63
|
Michael Daum
| AVIP, Altera, Altera VIP Suite, Camera Stream, Cyclone V SoC, Development Kit, Linux, QT, SATA Host Controller, SATA IP, SoC, SoM, Video Application, iWave, machine vision, sata, video overlay
iW-RainboW-G17D Altera Cyclone V SoC Development Board

iW-RainboW-G17D Altera Cyclone V SoC Development Platform
Block Diagram

Block Diagram FPGA

Development Platform Block Diagram
* Cyclone V SoC Qseven SOM:
- Cyclone V SOC 5CSXFC6
- 512MB HPS DDR3 RAM
- 256MB FPGA DDR3 RAM
- 10/100/1000 Ethernet PHY
- 4 Port USB2.0 HUB
- On SOM µSD Slot
- JTAG Header for FPGA
- OS: Linux 3.10
* Qseven Carrier Board:
- Standard SD - 1 Port (Boot & OS Storage)
- SATA 3.0 - 1 Port
- Debug Console through Micro USB
- Data UART - 1 Port
- CAN – 1 Port
- USB 2.0 Host - 3 ports
- 10/100/1000 Ethernet - 1 Port
- PCIe x1 Slot
- AC’97 codec- Audio IN/OUT Jacks#
- LVDS – 2 Port
- TV IN
- 7" TFT Display (800x480) with Capacitive Touch
- 2nd LVDS Connector
- PWM
- JTAG Header
- Operating Temperature: 0 to 55oC
- Form Factor: Nano-ITX (120mmX120MM)
- Power Input: 12V
- Quick customization & Technical Support
- Quick time to market
- Board Support Package Available
- Long term support, 5+ years
* Many More to come...
For specific details and queries: