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Information abut latest bootloaders for Cortex A9 based SoC FPGA devices
Table of Contents
This is a short guide showing how to connect the DS-5 Headless Debugger to Altera SoC Hardware
This is a short guide showing how to connect the DS-5 Headless Debugger to Altera SoC Hardware
Command Line Arguments
The following describes the command line arguments (--cdb-entry and --cdb-entry-param) of the ARM Headless Debugger.cdb-entry Argument
The table below shows the --cdb-entry command line argument required for each Altera SoC device| SoC Device | Debug Mode | Configuration Database Entry (cdb-entry) |
| Cyclone V SoC | Bare Metal | "Altera::Cyclone V SoC (Dual Core)::Bare Metal Debug::Bare Metal Debug::Debug Cortex-A9_0::USB-Blaster" |
| Arria V SoC | Bare Metal | "Altera::Arria V SoC::Bare Metal Debug::Bare Metal Debug::Debug Cortex-A9_0::USB-Blaster" |
| Arria 10 SoC | Bare Metal | "Altera::Arria 10 SoC::Bare Metal Debug::Bare Metal Debug::Debug Cortex-A9_0::USB-Blaster" |
| Cyclone V SoC | Linux Application | "Altera::Cyclone V SoC (Dual Core)::Linux Application Debug::Linux Application Debug::Download and debug application::USB-Blaster" |
| Arria V SoC | Linux Application | "Altera::Arria V SoC::Linux Application Debug::Linux Application Debug::Download and debug application::USB-Blaster" |
| Arria 10 SoC | Linux Application | "Altera::Arria 10 SoC::Linux Application Debug::Linux Application Debug::Download and debug application::USB-Blaster" |
cdb-entry-param/rvi_address Argument
The table below shows the name of the USB Blaster for each Altera SoC board or development kit. These values are passed to the rvi_address parameter using the --cdb-entry-param command line argument.| Board | rvi_address |
| Altera Atlas SoC | DE-SoC on localhost [USB-1]:DE-SoC USB-1 |
| Arrow Cyclone V SoCKit | CV SoCKit on localhost [USB-1]:CV SoCKit USB-1 |
| Altera Cyclone V SoC Development Kit | USB-BlasterII on localhost [USB-1]:USB-BlasterII USB-1 |
| Altera Arria V SoC Development Kit | USB-BlasterII on localhost [USB-1]:USB-BlasterII USB-1 |
| Altera Arria 10 SoC Development Kit | USB-BlasterII on localhost [USB-1]:USB-BlasterII USB-1 |
Example Command Lines
Example Cyclone V SoC Bare Metal Command line (Using the DE0-Nano-SoC):
debugger --cdb-entry="Altera::Cyclone V SoC (Dual Core)::Bare Metal Debug::Bare Metal Debug::Debug Cortex-A9_0::USB-Blaster" --cdb-entry-param="rvi_address=DE-SoC on localhost [USB-1]:DE-SoC USB-1"
Example Arrow Cyclone V SoCKit Bare Metal Command line (Using the Arrow SoCKit):
debugger --cdb-entry="Altera::Cyclone V SoC (Dual Core)::Bare Metal Debug::Bare Metal Debug::Debug Cortex-A9_0::USB-Blaster" --cdb-entry-param="rvi_address=CV SoCKit on localhost [USB-1]:CV SoCKit USB-1"
Example Cyclone V SoC Bare Metal Command line (Using the Altera Arria 10 SoC Development Kit):
debugger --cdb-entry="Altera::Arria 10 SoC::Bare Metal Debug::Bare Metal Debug::Debug Cortex-A9_0::USB-Blaster" --cdb-entry-param="rvi_address= USB-BlasterII on localhost [USB-1]:USB-BlasterII USB-1"
Launching the Debugger
The following shows an example of how to launch the debugger, connect to a board and download the preloader and U-boot executables on a Cyclone V SoC.- Start the SoCEDS and ARM Development Studio Embedded Command shell
- Cd to the “software/spl_bsp” directory (this is the output from the bsp-editor)
- Note: The following steps assume that the preloader and u-boot images have been built
- Notice in this directory there are two DS-5 scripts for debugging the preloader and uboot: preloader.ds and uboot.ds
- Run DS-5 headless debugger with the following command:
- debugger --cdb-entry="Altera::Cyclone V SoC (Dual Core)::Bare Metal Debug::Bare Metal Debug::Debug Cortex-A9_0::USB-Blaster" --cdb-entry-param="rvi_address=DE-SoC on localhost [USB-1]:DE-SoC USB-1"
- For Cyclone 5 at the debugger prompt, run the following commands (from the software/spl_bsp directory):
source –v preloader.ds loadfile uboot-socfpga/u-boot run
- For Arria 10 at the debugger prompt, run the following commands:
stop wait 5s reset system wait 5s set trust-ro-sections-for-opcodes off loadfile $sdir/uboot-socfpga/u-boot set debug-from *$entrypoint start restore $sdir/devicetree.dtb binary &_end b panic continue
References
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