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Agilex 5

• Linux GSRD Intel Simics Virtual Platform for Intel Agilex® 5 E-Series
• Zephyr* GSRD for Intel Agilex® 5 E-Series Simics Virtual Platform
• GHRD for Agilex 5 FPGA E-Series 065B Premium Development Kit

Golden System Reference Designs

Starting with the Quartus Prime 20.1, the GSRDs are documented on the following pages:

• Cyclone V SoC GSRD
• Arria 10 SoC GSRD
• Stratix 10 SoC L-Tile GSRD (24.1)
• Stratix 10 SoC H-Tile GSRD (24.1)
• GSRD for Agilex 7 F-Series Transceiver-SoC DevKit (P-Tile and E-Tile) (24.1)
• GSRD for Agilex 7 F-Series FPGA DevKit (2x F-Tile) (24.1)
• GSRD for Agilex 7 I-Series Transceiver-SoC DevKit (4x F-Tile) (24.1)
• GSRD for Agilex 7 FPGA M-Series Development Kit - HBM2e Edition (3x F-Tile & 1x R-Tile) (24.1)

Starting with Golden System Reference Design (GSRD) User Manuals 21.3, a single boot image approach is used, more details presented in Single Image Boot.

For pre 20.1 GSRDs, refer to Legacy Getting Started.

Bootloaders

• Building Bootloader for Cyclone V and Arria 10
• Building Bootloader for Stratix10 (24.1)
• Building Bootloader for Agilex 7 (24.1)
• Building Bootloader for Agilex 5 (24.1)

Configuring FPGA Fabric from Linux

• Agilex 7 Configuring FPGA Fabric From Linux
• Stratix10 Configuring FPGA Fabric From Linux

eMMC Boot

• Stratix 10 SoC with eMMC Storage on HPS
• Agilex 7 SoC With eMMC Storage On HPS

General Information

• Intel FPGA HPS Embedded Software Release Notes
• Intel® Simics® Simulator for Intel FPGAs Release Notes
• Git Introduction
• HOWTO Create a Device Tree

Remote System Update

• Agilex 7 SoC HPS Remote System Update
• Stratix 10 HPS Remote System Update
• Stratix10 RSU: Using Separate SSBL Per Bitstream
• Agilex 7 RSU: Using Separate SSBL Per Bitstream
• Remote System Update Compatibility

PCIe

• Cyclone V PCIe Root Port
• Arria 10 PCIe Root Port
• Arria 10, Cyclone V, Arria V PCIe Root Port
• Stratix 10 PCIe Root Port

Ethernet

• Cyclone V Main.SoC Triple Speed Ethernet
• Arria 10 Main.SoC Triple Speed Ethernet
• Cyclone V Main.SoC RGMII
• Arria 10 SGMII
• Stratix 10 SGMII
• Agilex 7 Main.SoC E-Tile 25Gbe IEEE1588 PTP
• Stratix 10 Main.SoC 10Gbe IEEE1588 PTP

Debugging

• Remote FPGA Debug for Stratix 10
• Remote FPGA Debug for Agilex 7
• Linux Kernel Debugging With DS-5
• Linux Application Debugging With DS5
• Arm Development Studio Examples

Other Projects

• Intel Agilex 7 SoC Secure Boot Demo Design (FPGA First)
• Intel Agilex 7 SoC Secure Boot Demo Design (HPS First)
• Application Development with Yocto eSDK
• Setting up and Using Bridges on Agilex 7 SoC
• Enabling new QSPI parts in U-Boot and Linux

Preloader & U-Boot

• HPS Boot Flow
• Preloader and U-Boot Source Code - Files & Folders
• Adding a New Board to Preloader & U-Boot
• QSPI / Serial NOR Flash Layout
• SDMMC Flash Layout

• Preloader: Generating the Preloader using Preloader Generator
• Preloader: Compiling the Preloader
• Preloader: Detailed Preloader Execution Flow
• Preloader: Inside Preloader Handoff Files
• Preloader: Preloader Clocking Customization
• Preloader: Adding a New Driver in Preloader
• Preloader: Boot from QSPI / Serial NOR Flash
• Preloader: Boot from FPGA
• Preloader: Loading U-Boot/Next Image From FAT Partition
• Preloader: Disabling SDRAM ECC
• Preloader: FPGA Programming from Preloader

• U-Boot: Getting U-Boot Source
• U-Boot: Compiling the U-Boot
• U-Boot: Adding a New Driver in U-Boot
• U-Boot: Programming QSPI from U-Boot console
• U-Boot: FPGA Programming from U-Boot
• U-Boot: Creating U-Boot script - u-boot.scr
• U-Boot: Loading U-Boot from DS-5
• [Creating all the bootloaders and a bootloader script with Intel EDS 18]
• Writing the FPGA configuration during boot with a script

Training and Tutorials

• SoC FPGA Training
• Altera SoC Workshop Series
  • Software Development Tutorial
  • Introduction to Linux Kernel Tutorial
  • Developing Linux Drivers Tutorial
  • HOWTO Create a Device Tree
• Intel Stratix 10 SoC - Helpful Links for New Users
• Mapping HPS Peripherals (e.g. CAN) over the FPGA fabric to FPGA I/O

GSRD Documentation - Arrow SoCKit Edition

• GSRD User Manual
• GHRD (Golden Hardware Reference Design) Overview
• Booting Linux Using Prebuilt SD Card Image
• Connecting to Board Web Server
• Connecting to Board Using SSH
• Running Sample Linux Applications
• Compiling Linux - Arrow SoCKit Edition
• GSRD v16.0 - SD Card - Arrow SoCKit Edition
• Compiling the Hardware Design
• FPGA Programming
• Generating and Compiling the Preloader
• Generating the Device Tree
• Using System Console
• Using Git Trees

Reference Design - Intel FPGA Devkit

• Arria 10 Golden Hardware Reference Design (GHRD)
• Cyclone V/Arria V GHRD
• Intel Stratix 10 Golden System Reference Design (GSRD)
• Arria 10 Golden System Reference Design (GSRD)
• Cyclone V/Arria V Golden System Reference Design (GSRD)
• Arria 10 SGMII Reference Design User Manual
• Arria 10 TSE reference design
• Arria 10 PCIe Root Port with MSI
• Arria V PCIe Root Port with MSI
• Cyclone V PCIe Root Port with MSI
• Arria 10 SoC Hardware Reference Design That Demonstrates Partial Reconfiguration
• Reference Design Release Tags

Overviews and References

• SoC FPGA Overview - What is an SoCFPGA?
• Embedded Linux Beginners Guide
• Altera Git Repositories
• Cyclone V SoC Reference Links

Building Linux

• Embedded Linux Beginners Guide
• Yocto / Angstrom on SoCFPGA
• Buildroot on SoCFPGA
• Ubuntu Core for SoCFPGA
• Ubuntu Core For SoC FPGA (Arrow SoCKit)
• Altera SoC LTSI Kernel
• Altera SoC LTSI Kernel with Preempt-RT
• Compiling Linux - Arrow SoCKit Edition

Building Linux with the Yocto Project

• Getting started with Yocto Project
• Layer for the Yocto project to access the FPGA Manager with Linux commands
• Adding Python pip-packages (PyPI) to the Yocto Project
• rsYocto: Embedded reference Linux developed for Intel SoC-FPGAs with the Yocto Project
• BootImageGenerator= Python Script to automatically generate a bootable Image file

Booting

• Boot Flow
• Booting from QSPI Flash
• Programming QSPI Flash
• Booting from FPGA
• Booting From Network with TFTP/NFS
• BootImageGenerator= Python Script to automatically generate a bootable Image file

Debugging

• Using DS-5 Headless Command Line Debugger with Altera SoCs
• Using System Console

FPGA Programming

• FPGA Programming from HPS Software
• FPGA Programming with Quartus II Programmer
• Writing the FPGA configuration during boot with a script
• Building a application to write the FPGA configuration with a single Linux command
• FPGA Programming and Interacting with a Web interface running on the HPS

Example Designs

• Device Wide AMP
• Arria V PCIe Root Port with MSI
• Cyclone V PCIe Root Port with MSI
• CycloneV SGMII Example Design
• Cyclone V SoC Triple Speed Ethernet Design Example
• Cyclone V RGMII Example Design

Other Documents

• Nios II Linux User Manual
• Using USB Blaster / USB Blaster II under Linux
• Getting Started With The Altera Development Kit
• Getting a DS-5 Altera Edition (AE) or Community (Free) License
• Git Web
• Android Documentation
• SoC Device Resources
• SoCFPGAEcosystem
• PreloaderNotes
• 13.0sp1 DS-5 Installation
• NiosIIUCOSIIApplicationSoftwarePortingToARMCortexA9Linux
• SoC FPGA Benchmarking
• Installing DS-5 On "Unsupported" Linux Distros
• CV/AV - Supported Flash Devices (external link)
• A10 - Supported Flash Devices (external link)
• Nios V/m Zephyr Design Example - Hello World
• Zephyr Driver for Intel FPGA Embedded Peripherals IP
• Nios V/g Zephyr Design Example - Hello World (Work In Progress)

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