AUDIO SUPPORT ON CYCLONE V SOC KIT

Introduction

This project demonstrates the inclusion of audio support with Xillinux for CYCLONE V SoC Kit. Xillinux is a graphical Linux distribution for the SoCKit board, intended as a platform for the development of mixed software / logic projects. The addition of this audio support enables the SoC kit for building any application that requires a sound card like Audio Video Player.

Figure 1: Cyclone V Soc Connected to a Speaker to deliver Audio

Generating new IP core from the IP Core Factory

STEP1:

• Sign up into xillybus.com using the link: http://xillybus.com/ipfactory/

STEP2:

• Click on “ add a new core”. It will take to the following window.

Figure 2: IP Core Factory Window to create a new IP Core

• Enter the IP core’s name. Example: audio_cyclonev_sockit.
• Select target device family from the drop down list as Altera Cyclone V SOC.
• Then click on “Create!”

STEP3:

• The next window gives the list of device files for the created IP Core.
• In order to add a new device file click on “ Add a new device file”.

Figure 3: Window displaying the Device files of an IP Core

STEP4:

• Add the required two device files: xillybus_audio and xillybus_smb with the parameters as shown below.
• xillybus_smb device file is used to instantiate the transaction on the chip’s I2C bus to program the audio chip.
• xillybus_audio device file enables the data transport.

Parameter	Xillybus_audio	Xillybus_smb
Direction	Bidirectional	Bidirectional
Use	Data acquisition/Play back	Command and status
Data_width	32	8
Expected Bandwidth	0.2 Mbytes/s	0.01 Mbytes/s
Buffering	10 ms	-
Autoset internals	Checked	Checked

Figure: 4 Creation of xillybus_audio Device file

Figure: 5 Creation of xillybus_smb Device file

STEP5: • When the device files are ready, from the status of Core Summary, click on “ generate core”.

Figure: 6 Generation of Audio IP Core

STEP6:

• To check the status of the generated core, click on “My saved IP cores “.

  

Figure: 7 Generated IP Core is ready to Download

• Click on “Download” of corresponding IP core.
• The folder will be downloaded with the name corebundle- followed by IP core name. Example: corebundle-audio_cyclonev_sockit

Verilog Source file changes

1. Download the FPGA bundle for Altera’s tool from the link below: http://xillybus.com/xillinux The zip file will be named with xillinux_eval_sockit_1.2.

2. Follow the instructions to generate the processor’s wrapper and raw bitstream file on http://xillybus.com/downloads/doc/xillybus_getting_started_sockit.pdf {Section 3.3 and 3.4 of the document}

3. After the new IPCore (corebundle-audio_cyclonev_sockit) is generated, follow the instructions from the README file.

i) Replace the existing xillybus.v file with the one in this bundle. Replace \xillinux-eval-sockit-1.2\xillinux-eval-sockit-1.2\verilog\src\xillybus.v with \corebundle-audio_cyclonev_sockit\xillybus.v

ii) Replace the xillybus_core.qxp file in the demo bundle's core/ subdirectory with the one in this bundle. Replace \xillinux-eval-sockit-1.2\xillinux-eval-sockit-1.2\core\xillybus_core.qxp with \corebundle-audio_cyclonev_sockit\xillybus_core.qxp

iii) Edit xillydemo.v (or xillydemo.vhd) to reflect the desired application of this custom IP core. This IP core has to reflect i2s_audio.v and smbus.v files from Zybo demo bundle. So add these two files to \xillinux-eval-sockit-1.2\xillinux-eval-sockit-1.2\verilog\src.

• Replace the fifos in the i2s_audio.v and smbus.v with the scfifo.

Instantiate scfifo instead of fifo_32x512 in i2s_audio.v file and fifo_8x2040 in smbus.v file.

• Edit the instance altera_pll in the xillybus.v file to generate an extra clock of 12 MHz frequency.
• Add audio_mclk as an output in the port_list of xillybus.v module. Modify clk_clk signal to a 2 bit vector of out_clk. Assign out_clk[0] to the soc_system’s clk and out_clk[1] to the audio_mclk.
• Instantiate i2s_audio, smbus in the xillydemo.v file.
• Disconnect the audio_mclk from the i2s_audio module and connect from the xillybus instance in the xillydemo.v file.

Testing the Audio Support

STEP1:After the source file changes are done, follow the instructions onthe linkhttp://xillybus.com/downloads/doc/xillybus_getting_started_sockit.pdf to generate theraw bitstream file {section 3.4 of the document}.

STEP2:Follow the steps in Section 3.5 from the given linkhttp://xillybus.com/downloads/doc/xillybus_getting_started_sockit.pdf to load the microSD with the image and Section 3.6 to copy the soc_system.rbf file into the micro SD card.

STEP3: Download the sound configuration files.

STEP4: Copy the soundconfig.zip to “audiosupport” directory in the Micro SD card file system home folder. Execute the following commands on shell prompt.

~#cd /home/audiosupport/

~audiosupport#unzip soundconfig.zip

~audiosupport#cd soundconfig ~soundconfig#cp default.pa /etc/pulse/

~soundconfig#cp module-file-sink.so /usr/lib/pulse-1.1/modules/

~soundconfig#cp xillinux-sound.conf /etc/init/

~soundconfig#mkdir /usr/local/bin

~soundconfig#cp xillinux-sound /usr/local/bin/

~soundconfig#chmod 777 /usr/local/bin/xillinux-sound

~soundconfig#cp altera_sound_setup.pl /usr/local/bin/

~soundconfig#chmod 777 /usr/local/bin/altera_sound_setup.pl

STEP5: Reboot the board and the sound card will be detected.

STEP6: Copy any *.wav audio file to the micro SD card.

STEP7: /dev/xillybus_audio can be written as below: ~#cat front_center.wav > /dev/xillybus_audio

Conclusion

With the addition of audio support, the Cyclone V SoC Kit with xillinux development platform is easy to build a complete design of an application where the FPGA logic and the Linux based software go together.

References

• http://xillybus.com/xillinux : To download the Demo bundle for Altera Cyclone V SoC Kit and the Micro SD card image.

• http://xillybus.com/downloads/doc/xillybus_getting_started_sockit.pdf: Provides the information about the demo bundle implementation.

• FPGA bundle for Altera’s tool