Hardware Design Overview

The hardware design is based upon the Cyclone V Golden Hardware Reference Design. This design enables FPGA2SDRAM interfaces 0, 1 and 2. Each port has an AXI Traffic Generator and an AXI Monitor IP core connected. The AXI Traffic Generator generates both read and write traffic. The AXI Monitor counts transaction, idle and throttle cycles as well as transaction minimum and maximum latencies.

To use the hardware design and the example application with the Cyclone V SoC Dev kit:

1. Download the hardware design and uncompress.
2. Build the design and copy the resultant .rbf file to your GSRD sdcard image in the FAT partition.
3. Download the software source and uncompress (see below)
4. Copy the source and cross compile the output to the Linux Root File System.
5. Run the altddr_perfmon executable (more instructions below).

IP Components

The following is a list of the IP Components used in and included with the hardware design.

AXI Traffic Generator IP Core Overview

The AXI Traffic Generator generates both read and write traffic.

Features:

• Separate Read and Write transaction generation enables. Reads and Writes can be enabled separately.
• Configurable data width (32,64,128,256)
• Configurable transaction address
• Configurable address width

AXI Traffic Generator IP Core Registers Address Map

Address Offset	Name	Read/Write	Reset Value	Description
0x0000	CONTROL	R/W	0	Bit [0]: Read Enable 1: Enables read transaction traffic 0: Disables read transaction traffic Bit [1]: Write Enable 1: Enables write transaction traffic 0: Disables write transaction traffic Bit[4]: Read Ready Enable This bit enables/disables the rready only (does not adjust the arvalid). 1: Enables read ready 0: Disables read ready
0x0004	TRAFADDR	R/W	0x3fff_0000	Bits[0-31]: Traffic Address This is the address used for both read and write transactions. A 64KByte range is used for the transactions (0x0000 - 0xFFFF). The upper 16bits of this address are used to set the 64KByte window into external memory. The lower 16bits are used to set the starting address. The read and write address counters will wrap at the 64KByte boundary.

AXI Traffic Generator IP Core Parameters

The following is the list of all the parameters of the AXI Traffic Generator IP core.

• AXI_ADDR_WIDTH: Sets the width of the AXI address buses (axi_m0_araddr and axi_m0_awaddr). The default value is 32.
• AXI_DATA_WIDTH: Sets the width of the AXI data buses (axi_m0_rdata and axi_m0_wdata). The default value is 64. Valid Range is {32,64,128,256}.
• AXI_USER_WIDTH: Sets the width of the AXI user buses (axi_m0_aruser and axi_m0_aruser). The default value is 5. Valid Range is {1-16}.
• AXI_BURST_SIZE: Sets the burst size encoding. The default value is 3 (AXI Burst of 8).

AXI Monitor IP Core Overview

The AXI Monitor counts transaction, idle and throttle cycles as well as transaction minimum and maximum latencies.

Features:

• Separate Counter Resets
• Read and Write Latency Counters. The Latency of the last transaction, min and max latencies are captured.
• Configurable data width (32,64,128,256)
• Configurable address width

AXI Monitor IP Core Registers Address Map

Address Offset	Name	Read/Write	Reset Value	Description
0x0000	CONTROL	R/W	0	Bit [0]: Enable 1: Enables the monitor 0: Disables the monitor Bit [4]: Read Data Counter Reset 1: Resets the read data transaction counter to zero 0: Clears the read data transaction counter reset. Bit [5]: Read Idle Counter Reset 1: Resets the read data idle cycle counter to zero 0: Clears the read data idle cycle counter reset. Bit [6]: Read Master Throttle Counter Reset 1: Resets the read data master throttle cycle counter to zero 0: Clears the read data master throttle cycle counter reset. Bit [7]: Read Slave Throttle Counter Reset 1: Resets the read data slave throttle cycle counter to zero 0: Clears the read data slave throttle cycle counter reset. Bit [8]: Read Latency Counter Reset 1: Resets the read data latency cycle counter to zero 0: Clears the read data latency cycle counter reset. Bit [12]: Write Data Counter Reset 1: Resets the write data transaction counter to zero 0: Clears the write data transaction counter reset. Bit [13]: Write Idle Counter Reset 1: Resets the write data idle cycle counter to zero 0: Clears the write data idle cycle counter reset. Bit [14]: Write Master Throttle Counter Reset 1: Resets the write data master throttle cycle counter to zero 0: Clears the write data master throttle cycle counter reset. Bit [15]: Write Slave Throttle Counter Reset 1: Resets the write data slave throttle cycle counter to zero 0: Clears the write data slave throttle cycle counter reset. Bit [16]: Write Latency Counter Reset 1: Resets the write data latency cycle counter to zero 0: Clears the write data latency cycle counter reset.
0x0004	RESERVED	R	0x0000_0000	RESERVED
0x0008	R_DATACOUNT	R	0x0000_0000	Bits[0-31]: Read Data Counter Number of cycles that rvalid and rready are both 1.
0x000C	R_IDLECOUNT	R	0x0000_0000	Bits[0-31]: Read Idle Counter Number of cycles that rvalid and rready are both 0.
0x0010	R_MTCOUNT	R	0x0000_0000	Bits[0-31]: Read Master Throttle Counter Number of cycles that rvalid is 0 and rready is 1.
0x0014	R_STCOUNT	R	0x0000_0000	Bits[0-31]: Read Slave Throttle Counter Number of cycles that rvalid is 1 and rready is 0.
0x0018	R_LCURCOUNT	R	0x0000_0000	Bits[0-31]: Read Current Latency Latency of last transaction.
0x001C	R_LMINCOUNT	R	0x0000_0000	Bits[0-31]: Read Minimum Latency Minimum latency since last monitor reset.
0x0020	R_LMAXCOUNT	R	0x0000_0000	Bits[0-31]: Read Maximum Latency Maximum latency since last monitor reset.
0x0024	W_DATACOUNT	R	0x0000_0000	Bits[0-31]: Write Data Counter
0x0028	W_IDLECOUNT	R	0x0000_0000	Bits[0-31]: Write Idle Counter
0x002C	W_MTCOUNT	R	0x0000_0000	Bits[0-31]: Write Master Throttle Counter
0x0030	W_STCOUNT	R	0x0000_0000	Bits[0-31]: Write Slave Throttle Counter
0x0034	W_LCURCOUNT	R	0x0000_0000	Bits[0-31]: Write Current Latency
0x0038	W_LMINCOUNT	R	0x0000_0000	Bits[0-31]: Write Minimum Latency
0x003C	W_LMAXCOUNT	R	0x0000_0000	Bits[0-31]: Write Maximum Latency

AXI Monitor IP Core Parameters

The following is the list of all the parameters of the AXI Monitor IP core.

• AXI_ADDR_WIDTH: Sets the width of the AXI address buses (axi_m0_araddr and axi_m0_awaddr). The default value is 32.
• AXI_DATA_WIDTH: Sets the width of the AXI data buses (axi_m0_rdata and axi_m0_wdata). The default value is 64. Valid Range is {32,64,128,256}.
• AXI_USER_WIDTH: Sets the width of the AXI user buses (axi_m0_aruser and axi_m0_aruser). The default value is 5. Valid Range is {1-16}

Building Example Linux Application

1. Download the included altddr_perfmon_src.tgz file (see below)
2. tar -xvzf altddr_perfmon_src.tgz
3. cd altddr_prefmon
4. make

Running Example Linux Application

1. cd altddr_perfmon
2. ./altddr_perfmon

Sample Output

Setting up Virtual Memory...Complete.

Sum of Weights for Each Priority
----------------------------------
Priority = 0: Sum Of Weights= 96
Priority = 1: Sum Of Weights= 0
Priority = 2: Sum Of Weights= 0
Priority = 3: Sum Of Weights= 0
Priority = 4: Sum Of Weights= 0
Priority = 5: Sum Of Weights= 0
Priority = 6: Sum Of Weights= 0
Priority = 7: Sum Of Weights= 64

Port Configuration
--------------------------------------------------------------------------------
Port 0 ( FPGA AXI S0 R, Avalon-MM S0 R/W): Priority = 0, Remap = 0, Weight = 16
Port 1 ( FPGA AXI S0 W, Avalon-MM S1 R/W): Priority = 0, Remap = 0, Weight = 16
Port 2 ( FPGA AXI S1 R, Avalon-MM S2 R/W): Priority = 0, Remap = 0, Weight = 16
Port 3 ( FPGA AXI S1 W, Avalon-MM S3 R/W): Priority = 0, Remap = 0, Weight = 16
Port 4 ( FPGA AXI S2 R, Avalon-MM S4 R/W): Priority = 0, Remap = 0, Weight = 16
Port 5 ( FPGA AXI S2 W, Avalon-MM S5 R/W): Priority = 0, Remap = 0, Weight = 16
Port 6 (               L3AXI 32-bit S0 R): Priority = 7, Remap = 0, Weight = 16
Port 7 (             MPU AXI 64-bit S0 R): Priority = 7, Remap = 0, Weight = 16
Port 8 (               L3AXI 32-bit S1 W): Priority = 7, Remap = 0, Weight = 16
Port 9 (             MPU AXI 64-bit S1 W): Priority = 7, Remap = 0, Weight = 16

Determining Throughput...Complete.

AXI/Avalon Bandwidth and Efficiency:
------------------------------------------------------------------
Interface 0 Read  Bandwidth   0.0 MB/s. Max BW 381.5 MB/s (0.0%)
Interface 0 Write Bandwidth   0.0 MB/s. Max BW 381.5 MB/s (0.0%)
Interface 1 Read  Bandwidth   0.0 MB/s. Max BW 381.5 MB/s (0.0%)
Interface 1 Write Bandwidth   0.0 MB/s. Max BW 381.5 MB/s (0.0%)
Interface 2 Read  Bandwidth 381.5 MB/s. Max BW 381.5 MB/s (100.0%)
Interface 2 Write Bandwidth   0.0 MB/s. Max BW 381.5 MB/s (0.0%)

Usage

Usage: altddr_perfmon [ARGUMENTS]

altddr_perfmon Reports the current bandwith and efficiency of the Altera
Multi-Port Front End of the Altera EMIF controller.

Arguments:
  -pPORT=NUM, --set-priority portPORT=NUM  Sets the Priority of port PORT
                                           to NUM. PORT must be between 0
                                           and 9. NUM must be between 0 and 7.
                                           -p0=1 and --set-priority port0=1
                                           both set the priority of port 0 to 1

  -wPORT=NUM, --set-priority portPORT=NUM  Sets the Weight of port PORT to NUM
                                           PORT must be between 0 and 9. NUM
                                           must be between 0 and 31. -w2=17
                                           and --set-weight port2=17 both set 
                                           the weight of port 2 to 17.

  -h, --help Display this help