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Multiprocessor Nios V/m system: creating your first GeMRTOS application
Quick Start Guide on how to create a multiprocessor system with Nios V processor and GeMRTOS support -
Intel® Agilex® 7 I-Series Transceiver-SoC Development Kit (4x F-Tile) System Example Design With IEEE1588 PTP (25GE/10GE 2-Port)
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Setting up and Using Bridges on Agilex 7 SoC
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Agilex 7 SoC With eMMC Storage On HPS
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Stratix 10 SoC with eMMC Storage on HPS
Table of Contents
Classified Topic
DevOps
04 July 2023
| MoranFarcas
Project
2.4" Touch LCD Painter Demo on Atlas-SOC
This demonstration shows how to implement the painter demonstration on 2.4" LCD with Atlas-SoC development board
Android for DE1-SoC Board
Android 4.3 image for DE1-SoC. Includes app that interfaces with FPGA to toggle LEDs.
Arria V PCIe Root Port with MSI
An example which implements a PCIe root port on an Altera Arria V SoC development board
Cyclone V SoC Triple Speed Ethernet Design Example
This design example demonstrates how to use Cyclone V SoC with Triple Speed Ethernet (TSE) example design release packages.
DE1-SoC ALSA audio
IP cores and Linux ALSA SOC device drivers to play sound on Terasic's DE1-SoC development board.
DE1_SOC_My_First_HPS
Help you understand how to create a Clanguage software design and run it on your ARM-included DE1-SoC development board.
29 July 2015
| JohnnyFan
DevBoard 3D & CNC
3D Printer Controller with Slicer System ( with Altera SoCFPGA )
Graphics on Altera MAX10 Arrow/Terasic DECA Board
Running graphics on DECA
HPS_2_FPGA
Data exchange between HPS & FPGA to send commands from HPS to FPGA
Multi-channel PWM Design using Macnica Helio.
This design demonstrates how to utilize the Macnica Helio SoC board to add multi-channel PWM (pluse width modulation) device.
OpenCL Mandelbrot Demo on Atlas-SoC
21 September 2015
| ChrisRauer
| Demo, Reference Design | atlas, cyclone5, cylconev, de0-nano-soc, demo, linux, mandelbrot, opencl
PCIe Root Port with MSI
An example which implements a PCIe root port on an Altera Cyclone V SoC development board and a PCIe end point on a Cyclone V development board
Stratix 10 SoC Design Example for 10Gbe with IEEE1588 PTP Capability (closed)
19 September 2022
| LuisLui85
| 10G, 1588, Ethernet, PTP, QSE, Quad speed ethernet, SoC, Stratix 10, Timestamp
Stratix 10 SoC Design Example for 10Gbe with IEEE1588 PTP Capability - Sustaining - User Manual
06 December 2022
| LuisLui85
| 10G, 1588, Ethernet, PTP, QSE, Quad speed ethernet, Stratix 10, Timestamp
Stratix 10 SoC Design Example for 10Gbe with IEEE1588 PTP Capability v21.2 (closed)
19 September 2022
| LuisLui85
| 10G, 1588, Ethernet, PTP, QSE, Quad speed ethernet, SoC, Stratix 10, Timestamp
Using CMSIS with Custom FPGA Logic
Describe format of CMSIS-SVD file, integrate the SVD file into the system, and expose the register of custom logic in the register view of DS-5.
Video Demonstration for Human Recognition
Detection of humans in input videos and drawing of rectangular frames from detected points on humans.
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