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Recent Changes
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Intel® Agilex® 7 I-Series Transceiver-SoC Development Kit (4x F-Tile) System Example Design With IEEE1588 PTP (25GE/10GE 2-Port)
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Stratix 10 SoC with eMMC Storage on HPS
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Stratix 10 PCIe Root Port with MSI
Reference Design on Stratix 10 Development Kit demonstrating a Gen3x8 Capable Root Port -
Agilex 7 SoC With eMMC Storage On HPS
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Stratix 10 HPS Remote System Update
HPS Driven Remote System Update Example for Stratix 10
GHRD modified to use only one external DDR3 memory chip
GHRD modified to use only one external DDR3 memory chip
| Board: | ArrowSoCKitEvaluationBoard |
|---|---|
| Tools Version: | 13.0.1 |
| State: | running |
| Members: | StevenKravatsky |
- Generate the QSYS system in QII 13.0 sp1. Using a QSYS system generated prior to sp1 will not work.
- Add the .qip file to the project prior to compile in QII 13.0 sp1
- Add the sdram sdc file to the project to pass timequest
- Do the analysis and synthesis in Quartus
- Run the pin placement TCL script – as per the SoCKit workshop
- Full Quartus compile in QII 13.0 sp1
- Generate the preloader source files using bsp-editor run in the embedded command shell in the QII 13.0 sp1 install directory tree
- Make the preloader from the embedded command shell in the QII 13.0 sp1 install directory tree
- Rebuild u-boot. Modify the source to account for half the DDR3 memory
a. Open /include/configs/socfpga_cyclone5.h
b. Change the following
#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET #define PHYS_SDRAM_1_SIZE 0x80000000
#else
#define PHYS_SDRAM_1_SIZE 0x40000000
#endif to be #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
#define PHYS_SDRAM_1_SIZE 0x80000000
#else
#define PHYS_SDRAM_1_SIZE 0x20000000
#endif c. rebuild u-boot
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