State: planned
Members: StevenKravatsky

Overview

This reference design is an example that shows how to use both the HPS and FPGA portion of the SoC concurrently to implement a complex function. The video decode and server portion of the design are implemented on the dual core Cortex-A9 processor while the alpha blending mixer is implemented in the FPGA.

Two streams of MPEG2 encoded video are read from the SD card file system. They are then decoded to RGB video by the two ARM Cortex-A9 cores. The decoded video streams are then sent via DMA to the Video IP chain within the FPGA. The two video streams are mixed with a logo layer and a background layer and then sent to the video output block.

The video server and VIP demo were implemented quickly by taking advantage of open-source code such as libmpeg2, a MPEG 2 decoder. Standard Linux offerings including a file system management and threading were also utilized. In this system. Two 640x480 video files (.m2v) are read out of the SD card and decompressed for shipment to the frame buffer (DDR3) on the FPGA side. Note that both sides are utilizing their DDR3 controllers.

On the FPGA side, Altera's VIP suite was used to quickly implement an alpha blending mixer of a full HD background, "Moving Pictures" and a logo within the HD frame. Note that management of the VIP blocks (such as position) are also being handled by the ARM.

This reference design was created by Terasic.

To see a youtube demo click on the following link http://www.youtube.com/watch?feature=player_embedded&v=jko4n26ITrE

For more information please click on the link below..

http://sockit_support.terasic.com

To obtain the design source code please send an email to support@terasic.com

Block Diagram

VIP.jpg

Demo Instructions

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