Overview

This design is based on The Golden Hardware Reference Design (GHRD) for Sodia Evaluation Board.
About the GHRD description refer to here.

Added interfaces and components is following:

• Digital Visual Interface (DVI) output interface
  • Frame Reader conmpnent
  • Color Plane Sequencer II component
  • Clocked Video Output II component

Note: Contents in this page that highlighted in red and bold font is added for this design.

Block Diagram of HW Design

MPU Address Maps

This section presents the address maps as seen from the MPU (A9) side. Please note that address map is changed from v16.1. This page described NEW address map. For legacy address map [ Click Here].

HPS-to-FPGA Address Map

The memory map of soft IP peripherals, as viewed by the microprocessor unit (MPU), starts at HPS-to-FPGA address offset 0xC000_0000. The following table lists the offset of each peripheral in the FPGA portion of the SoC.

Peripheral	Qsys Address Offset	MPU View	Size (bytes)	Attribute
onchip_memory2_0	0x0	0xc000_0000	64K	On-chip RAM as scratch pad

Lightweight HPS-to-FPGA Address Map

The memory map of system peripherals in the FPGA portion of the SoC as viewed by the MPU, which starts at the lightweight HPS-to-FPGA base address 0xFF20_0000, is listed in the following table.

Peripheral	Qsys Address Offset for mm_bridge	Qsys Address Offset from mm_bridge	MPU View	Size (bytes)	Attribute
jtag_uart	0x4_0000	0x2_0000	0xff26_0000	8	JTAG UART console
sysid_qsys	0x4_0000	0x2_0008	0xff26_0008	8	Unique system ID
led_pio	0x4_0000	0x2_0040	0xff26_0040	8	LED output display
dipsw_pio	0x4_0000	0x2_0080	0xff26_0080	8	DIP button input
button_pio	0x4_0000	0x2_00c0	0xff26_00c0	8	Push button input
vfr	0x4_0000	0x2_0100	0xff26_0100	128	Frame Reader (for DVI output)
ILC	0x4_0000	0x3_0000	0xff27_0000	256	Interrupt Latency Counter

JTAG Master Address Map

There are two JTAG master interfaces in the design, one for accessing non-secure peripherals in the FPGAfabric, and another for accessing secure peripheral in the HPS through the FPGA-to-HPS Interface.

The following table lists the address of each peripheral in the FPGA portion of the SoC, as seen through the non-secure JTAG master interface.

Peripheral	Qsys Address Offset for mm_bridge	Address Offset	Size (bytes)	Attribute
onchip_memory2_0		0x0	64K	On-chip RAM
jtag_uart	0x4_0000	0x0002_0000	8	JTAG UART console
sysid_qsys	0x4_0000	0x0002_0008	8	Unique system ID
led_pio	0x4_0000	0x0002_0040	8	4 LED outputs
dipsw_pio	0x4_0000	0x0002_0080	8	2 DIP switch inputs
button_pio	0x4_0000	0x0002_00c0	8	2 push button inputs
vfr	0x4_0000	0x0002_0100	128	Frame Reader (for DVI output)
ILC	0x4_0000	0x0003_0000	256	Interrupt Latency Counter

Interrupt Routing

The HPS exposes 64 interrupt inputs for the FPGA logic. The following table lists the interrupts from soft IP peripherals to the HPS interrupt input interface.

Peripheral	Interrupt Number	Attribute
dipsw_pio	f2h_irq0[0]	2 DIP switch inputs
button_pio	f2h_irq0[1]	2 push button inputs
jtag_uart	f2h_irq0[2]	JTAG UART
cvo_ii	f2h_irq0[3]	Clocked Video Output
vfr	f2h_irq0[4]	Frame Reader

The interrupt sources are also connected to an Interrupt Latency Counter module in the system, which enables System Console to be aware of the interrupt status of each peripheral in the FPGA portion of the SoC.

Reference Designs

Item	Rev.	Download	Note
HW Reference Design	v1.1	sodia_dvi_ghrd_v16.1.0.zip	Quartus Prime Standard Edition v16.1 This design is based on the HW Reference Design v1.1 (sodia_ghrd_v16.1.0.zip)
HW Reference Design	v1.0	sodia_dvi_v15.1.2.zip	Quartus Prime Standard Edition v15.1.2
Linux SD Card Image	-	Uploaded to the another page. [ Click Here ]	For more information, see "Projects > Sodia Debian Base Desktop Image" in this website.