Introduction

The Three Gigabit Ethernet Solution enables three 10/100/1000 Ethernet RGMII PHY ports. One port (J7) is supported via HPS GigE interface and other two ports (J5 and J6) are implemented in FPGA using Altera Triple Speed Ethernet (TSE) and Modular Scatter-Gather Direct Memory Access (mSGDMA) IP Cores for data transfer within the system. The project runs on a Bach Pro-Audio Development Kit from Coveloz that features a Cyclone V SoC based System-on-Module board plugged into a Pro-Audio development board, many peripherals of which include the ethernet ports (J5, J6 and J7) that use Micrel PHYs.
The solution also includes support for an HPS UART USB interface. Note: the audio interfaces located on the Coveloz Pro-Audio Development Board are not supported in this project.

Development Environment

Hardware	Coveloz Networked Pro-Audio Development Board
FPGA	Altera Quartus Prime version 15.1.0 build 185 Altrea SoC EDS 15.1.0 build 185
Software	Linux Ubuntu 14.04 LTS or Linux CentOS release 6.7 Buildroot version 2014.08

Block Diagram

NOTE: The above diagram only includes two Gigabit Ethernet ports that are designed using TSE with DMA modules and does not include HPS Ethernet port.

Qsys Top Design Components:

• HPS
• System ID module
• TSE with DMA module 0
• TSE with DMA module 1
• Clock PLL (provides 50MHz, 2.5MHz, 25MHz, and 125MHz clocks from 50MHz)
• Interrupt Capture Module
• Avalon-MM Pipeline Bridge
• JTAG to Avalon Master Bridges for:
  • HPS
  • FPGA
  • DMA Descriptor

TSE with DMA Submodule:

• Coveloz Gigabit Ethernet Clock Divider (provides the correct TX clock to PHY based on speed settings)
• Altera TSE module with RGMII and MDIO
• Tx modular Scatter-Gather DMA
• Rx modular Scatter-Gather DMA

Release Contents

File	Description
bin_covbachsdk.tar.gz	Binaries archive: pre-built 1.8 GB SD image and all of the files required to rebuild it.
hw_covbachsdk.tar.gz	Hardware archive: all of the files necessary to rebuild FPGA binaries
sw_covbachsdk.tar.gz	Software archive: achive of software patches necessary to rebuild Linux firmware

Quick Start Guide

1. Program the μSD card using the provided SD image in bin folder

   $ sudo dd if=sd_card_image_covbachsdk.bin of=<sdcard device> bs=1M

2. Setup the BACH Pro-Audio Development Board
   • Insert BACH SOM (J1)
   • Insert jumper in the bottom two pins of J2 (pins 29 and 30)
   • Insert uSD card into the board (J11)
   • Insert Ethernet cables (J5, J6 and/or J7)
   • Connect USB cable between UART USB port (J9) and host computer.
3. Plug in the power source to J4 power connector (NOTE: there is no power on/off button on the board. The board has a Cold Reset switch (SW1))
4. Configure Serial Connection between the board and host PC to 115200 bps 8-N-1 with NO hardware or software flow control. The detailed instructions can be found in 'Configuring Serial Connection' section of Golden System Reference Design (GSRD) User Manual
5. Kernel will bring up all three ethernet ports (eth0 (J7), eth2 (J5) and eth1 (J6) and will attempt to assign IP addresses to all of them by running DHCP.
6. Login in as root (password - root) after booting is complete.
7. Make sure that Ethernet ports are operational (either by checking the left LED on the Ethernet connector or by checking the link status with ethtool)If the link is not up, re-insert the ethernet cable, and when link is up, run

   # udhcpc -i ethx 

   where x stands for eth connection

Available Test/Configuration Tools

• ping
• ethtool
• iperf
• tcpdump
• scp
• ssh
• udhcpc
• fpgareg_read → read access to HPS bridge (ex. <fpgareg_read 10000> will return SystemID of the FPGA)
• fpgareg_write → write access to HPS bridge (write capabilities will depend on individual FPGA register setup)
• phy-dump → register dump of PHY device
• phy-write → write access to PHY device register

The tests described in Ethernet Design Example Demo Testing can be used to test Three Gigabit Ethernet Ports Solution.

Development Flow

Hardware Development Flow

The hardware development flow follows the Golden System Reference Design (GSRD) procedure for Compiling Hardware Design.

All of the files required to rebuild .sof and .rbf files are provided in the Hardware Achive ( hw_covbachsdk.tar.gz)

Directory	Description
par	Contains project files, such as .qpf and .qsf, as well as constraints and output files
qsys	.qsys files to regenerate the qsys components
src	Verilog files for Coveloz modules used in the design

Software Development Flow

The software used in the design is built using buildroot version 2014.08 and Linaro ARM 2014.05 toolchain (arm-linux-gnueabihf). Please note that toolchain is downloaded and installed automatically by the buildroot. The U-boot and preloader are generated using Altera SoC EDS tools and build with Linaro ARM 2014.05 toolchain.

The Software Achive ( sw_covbachsdk.tar.gz) includes three files:

File	Description
buildroot_covbachsdk.patch	Patch to apply on top of buildroot repository to add configuration file for the Coveloz Development Board
linux-socfpga_covbachsdk.patch	Patch to apply on top of linux repository to add Linux compile configuration file for the Coveloz Development Board and to enable PHY ioctl calls
rootfs_overlay_covbachsdk.tar.gz	Linux kernel initialization scripts and additional test software binaries

1. Generating the Device Tree Blob

The Device Tree source and blob files are generated using sopc2dts utility provided in Altera SoC EDS (https://rocketboards.org/foswiki/view/Documentation/GSRD151DeviceTreeGenerator)

Procedure:

1. Obtain cov_bach_sdk.sopcinfo file from /qsys folder of the solution's Hardware Achive ( hw_covbachsdk.tar.gz).
2. Start an Embedded Command Shell. The instructions below assume that Altera EDS is installed in ~/altera/15.1 directory

3. $ ~/altera/15.1/embedded/embedded_command_shell.sh

4. Run the Device Tree Generator from the /qsys folder of the solution's Hardware Achive to generate device tree blob file

5. $ sopc2dts --input cov_bach_sdk.sopcinfo \
   --output socfpga.dtb \
   --type dtb \
   --board cov_bach_sdk_board_info.xml \
   --bridge-removal all \
   --clocks 

To generate the device tree source, specify --type argument as dts and --output argument as socfpga.dts in the above command.

NOTE: The sopc2dts command will print following warnings: "Component enet_pll of class altera_pll is unknown", "Component tse_0_cov_core_gbe_clk_div_0 of class cov_core_gbe_clk_div is unknown", and "Component tse_1_cov_core_gbe_clk_div_0 of class cov_core_gbe_clk_div is unknown". These warnings can be safely ignored for this design.

2. Compiling Linux Distribution

The Linux image and Root Filesystem for the solution are compiled using buildroot utility.

Procedure to compile Linux image and root filesystem:

1. Create the solution's software directory by extracting the software archive ( sw_covbachsdk.tar.gz)

   $ tar -xvf sw_covbachsdk.tar.gz
   $ cd sw_covbachsdk

2. Obtain buildroot version 2014.08 from buildroot.org

   $ git clone https://git.buildroot.net/buildroot
   $ cd buildroot
   $ git checkout tags/2014.08 -b buildroot_2014.08

3. Apply buildroot_covbachsdk.patch on top of the local buildroot directory

   $ cd ..
   $ patch -d buildroot/configs/ -p2 < buildroot_covbachsdk.patch

4. Obtain the Linux socfpga ltsi 3.10 release from Altera opensource github repository

   $ git clone https://github.com/altera-opensource/linux-socfpga
   $ cd linux-socfpga
   $ git checkout remotes/origin/socfpga-3.10-ltsi

5. Apply the linux-socfpga_covbachsdk.patch on top of the local linux distribution.

   $ cd ..
   $ patch -d linux-socfpga/ -p1 < linux-socfpga_covbachsdk.patch

6. Unzip the rootfs_overlay_covbachsdk.tar.gz into the cov_bach_sdk_sw directory

   $ tar -xvf rootfs_overlay_covbachsdk.tar.gz

7. Go to buildroot directory and configure the make to build cov_bach_sdk

   $ cd buildroot
   $ make covbachsdk_defconfig

8. Build the Linux distribution

   $ make

The buildroot downloads all of the necessary files, including the toolchain and packages, builds the kernel images and overlays the default rootfs with the files from rootfs_overlay_covbachsdk/ directory. The output images (zImage and rootfs.ext3) are located in buildroot/output/images folder

To learn more about buildroot, please go to https://buildroot.org/docs.html

3. Generating Preloader and U-Boot Images

The solution is using U-Boot SPL 2013.01.01, which is generated with BSP-Editor Altera SoC EDS utility and it is built using arm-linux-gnueabihf Linaro ARM toolchain.

Procedure:

1. Generate and compile preloader
   The preloader is generated following the GSRD instructions https://rocketboards.org/foswiki/view/Documentation/GSRD151Preloader.
   The RTL handoff files are located in /par/hps_isw_handoff folder of Hardware Achive.
   NOTE: the CROSS_COMPILE setting in BSP-Editor should be set to arm-linux-gnueabihf- to facilitate building of Uboot
2. Point to the toolchain from the buildroot

   $ export CROSS_GCC=${BUILDROOT_DIR}/output/host/usr
   $ export PATH=$PATH:${CROSS_GCC}/bin
   $ export CROSS_COMPILE=arm-linux-gnueabihf-

3. Make the preloader: output preloader-mkpimage.bin

   $ cd par/software/spl_bsp
   <span style="font-size: 12.22px; line-height: 1.385em; background-color: #f6f6f6;">$ make</span>

4. Make the u-boot image: output u-boot.img

   $ cd uboot-socfpga
   $ make

4. Creating and Updating an SD Card

The steps for creating and updating the SD Card are outlined in the https://rocketboards.org/foswiki/view/Documentation/GSRD151SdCard. The solution's SD Card layout is identical to GSRD.

Using the make_sdimage.py tool at https://releases.rocketboards.org/2015.10/gsrd/tools/make_sdimage.py

$ cd bin_covbachsdk
$ sudo python make_sdimage.py \
    -f \
   -P preloader-mkpimage.bin,u-boot.img,num=3,format=raw,size=10M,type=A2 \
   -P rootfs.ext3,num=2,format=raw,size=1500M,type=83 \
   -P zImage,u-boot.scr,soc_system.rbf,socfpga.dtb,num=1,format=vfat,size=500M \
   -s 2G \
   -n sd_card_image_covbachsdk.bin

The default locations of the re-built binaries are

SD Card File	Default Location	Built Using...
preloader-mkpimage.bin	hw_covbachsdk/par/software/spl_bsp/	bsp-editor and Linaro cross-compiler
u-boot.img	hw_covbachsdk/par/software/spl_bsp/uboot-socfpga	bsp-editor and Linaro cross-compiler
rootfs.ext3	sw_covbachsdk/buildroot/output/images	buildroot
zImage	sw_covbachsdk/buildroot/output/images	buildroot
soc_system.rbf	hw_covbachsdk/par/output_files/cov_bach_sdk.rbf	Quartus Prime
socfpga.dtb	hw_covbachsdk/qsys/cov_bach_sdk.dtb	sopc2dts EDS tool

Please note that .rfb and .dtb files generated by the project has to be renamed before creating SD card image.

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Further Support

Please contact Coveloz for further assistance