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PCIe Root Port with MSI
An example which implements a PCIe root port on an Altera Cyclone V SoC development board and a PCIe end point on a Cyclone V development board
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An example which implements a PCIe root port on an Altera Arria V SoC development board
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Table of Contents
An example which implements a non-MSI PCIe root port on an Altera SoC development board
An example which implements a non-MSI PCIe root port on an Altera SoC development board
| Board: | AlteraSoCDevelopmentBoard |
|---|---|
| State: | planned |
| Members: | LFTAN, RocketHwong |
Please refer to this project for updated PCIe example design with MSI support
This example shows functionality of the HIP PCIe root port with HPS (ARM) as the host processor. It shows the entire design flow from Qsys/Quartus-II to device tree handoff to Linux application access.
There are two hardware configurations. The first configuration demonstrates DMA transfer throughput over PCIe Gen1 x4 link from either RP (read/write) or EP (read/write). The second configuration simply enumerates and configures an off-the-shelf PCIe Ethernet card to show general compatibility.
Application Note
This document describes how to use the PCIe Root Port design example on an Altera Cyclone V Development Board. The design example consists of Qsys projects and Linux software, which can be downloaded as described in the following sections.Qsys Projects
Three different root port Qsys designs are included for different size requirements (full, simplified, small).Software
This tar file includes all the source and binaries for Linux RP driver, EP driver, and Linux benchmark app.
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